AMD announced the first official details for the Milan-X chips – a modification of the EPYC Milan server processors with 3D-stacked L3 cache (dubbed 3D V-Cache), which can be up to 768 MB in size. That massive hunk of cache can speed up workloads by 50% on average. The way it works is that every Zen 3 chiplet inside the EPYC Milan-X processors will have 64 MB of 7 nm SRAM stacked on top, which is in addition the 32 MB of L3 that are already on the chiplet itself. Obviously, the final L3 capacity is tied to the number of chiplets and therefor to the number of processor cores. According...
Source: https://www.gsmarena.com/amd_unveils_epyc_milanx_processors_with_up_to_768mb_of_l3_cache_per_socket-news-51767.php
